1. Field of the Invention
The present invention relates to an input circuit preferred for an initial stage circuit such as a receiving circuit of a radio communication circuit, more particularly relates to an input circuit excellent in both of a low noise property and a high linearity by using bipolar transistors.
The present invention further relates to a phase adjustment circuit, more particularly relates to a phase adjustment circuit giving a constant range of adjustment and adjustment sensitivity and a good linearity and stability of adjustment without regard as to the clock frequency for controlling the apparatus to be adjusted.
The present invention further relates to a control signal generation circuit for generating a plurality of control signals which are selectively used in the phase adjustment etc. and analog-interpolated, more particularly relates to a control signal generation circuit giving a good linearity and stability in the control signal to be generated.
2. Description of the Related Art
In the initial stage of a radio communication circuit, for example, a very wide dynamic range is required. This is because it is necessary to handle a wide range of everything from extremely weak input signal conditions where the transmission side is remote to large input conditions where the transmission side is in close proximity.
As a circuit using bipolar transistor elements, an emitter ground circuit shown in FIG. 1A and a differential amplification circuit shown in FIG. 1B are generally used, but sufficiently satisfactory performances were not obtained by these circuit configurations of the related art.
First, while an emitter ground circuit is excellent in its noise characteristic, the linearity at the time of a large input is extremely poor. On the other hand, when adopting a differential amplification circuit, the linearity is improved somewhat, but the allowable maximum input level was about .+-.10 to 20 mV at most--which cannot be said to be a sufficient level. Further, by inserting a feedback resistor between the emitters, it is possible to improve the linearity, but in this case, there was the drawback that the noise characteristic was deteriorated.
Further, in a radio communication circuit etc. when a modulated signal of a narrow bandwidth is handled, among the non-linear components, particularly the odd number components are considered a problem. This is because in the mixed modulated components produced by a plurality of signals in a signal bandwidth, the mixed modulated components due to the even number non-linear components fall out of the bandwidth of the signal, but in contrast the mixed modulated components due to the odd number non-linear component may fall in the signal bandwidth. While a field effect transistor (FET) has a square characteristic, a bipolar transistor has an exponential characteristic, so the belief up to this point was that a bipolar transistor was considerably inferior in linearity.
Further, in an electronic apparatus such as a personal computer or a work station, the trend is for replacement of the cathode ray tubes (CRTs or Braun tubes) used as the displaying means to be replaced by liquid crystal displays (LCDs) and other flat panel displays. Further, in place of presentations by overhead projectors (OHPs) of the related art, presentations are now increasingly being made using projection type projectors which can be directly connected to personal computers to serve as their displays. Many of such projectors also use LCDs.
These displays use the same interfaces and connection methods as those of the CRT displays, therefore in current usage, analog RGB (red-green-blue) signals are transmitted. In the future, digital transmission will naturally be conceivable, but so long as CRT displays are the mainstream, transmission of analog RGB signals must be considered the basic assumption.
On the other hand, in an LCD or other flat panel display, a pixel is comprised by an independent unit and has a discrete structure unlike in a CRT display, therefore it is necessary to sample the signals transmitted in the analog format again and convert them to discrete signals. Signals from a personal computer are inherently discrete signals, so it is very wasteful to convert them to continuous signals and sample them again, but this is unavoidable so far as the assumption is the use of the interface of a CRT display.
FIG. 2 is a view of the configuration of a system where a display use output data from a personal computer 10 is output to an LCD 20 (first related art). The display use output digital data held in a video random access memory (RAM) 6 in the personal computer 10 is converted to an analog RGB signal by a digital-to-analog converter (D/A converter) and transmitted to the LCD 20 via an analog RGB cable 11.
In the LCD 20, the received analog RGB signal is subjected to .gamma. correction processing-for correcting the non-linear characteristic of the LCD elements and processing for the luminance and contrast, is sampled by a sample-and-hold circuit (S/H circuit) 22, and then converted to a parallel signal by a second signal processing unit 23 which is used to drive an LCD panel 24.
Here, a time corresponding to one pixel is referred to as a pixel clock and is about 20 to 100 MHz. Further, there are several types of structures of the elements constituting the LCD panel 24. For example, there are a super twisted nematic (STN) type and a thin film transistor (TFT) type providing thin film transistors in individual liquid crystal elements. Further, the TFT type includes a type using amorphous silicon and a type using polycrystalline silicon.
In the TFT type using polycrystalline silicon, a relatively high speed operation is possible. Therefore, for example, in the case of a viewfinder of a video camcorder or a small liquid crystal monitor or other LCD panel of at most about 200,000 pixels, it is possible to read the signal as it is based on the pixel clock. When it comes to the monitor of a personal computer 10, however, there are at least 300,000 pixels. Also, the frame frequency is considerably higher than that of a TV signal. Accordingly, not matter what structure is adopted, the signal cannot be input as it is based on such a high speed clock and displayed on the LCD panel 24. For example, in a TFT type using amorphous silicon, one horizontal scanning line's worth of a signal is converted once to a parallel signal and the signal written for every row.
Further, in a TFT type using polycrystalline silicon capable of performing a relatively high speed operation, a signal sent by the pixel clock frequency is converted to for example two to 12 parallel signals, the clock frequency used for reading is lowered, and the signals are input to the liquid crystal panel 24. Note that this processing is carried out at the sample-and-hold circuit 22 and the second signal processing unit 23.
Further, FIG. 3 is a view of the configuration of a system based on a different configuration where the display use output data from the personal computer 10 is output to an LCD 30 (second related art). In this related art, the analog RGB signal transmitted from the personal computer 10 via the analog RGB cable 11 is converted to a digital signal again by an analog-to-digital converter (A/D converter) 31, subjected to the processing of .gamma. correction etc. by the first signal processing unit 32, and then converted to parallel signals in which the clock frequency is lowered by a plurality of D/A converters 33-l to 33-n which are used to drive the LCD panel 34.
Next, an explanation will be made of the significance of the timing of the sampling operation and holding operation in the sample-and-hold (S/H) circuit 22 of the first related art. FIGS. 4A to 4D are timing chart of signals in the system of the first related art.
Assume that the output of the D/A converter 7 of the personal computer 10 changes at the rising edge of the pixel clock as shown in FIGS. 4A and 4B. Here, the output of the D/A converter 7 is ideally a sharp step-like waveform output as indicated by a dotted line of FIG. 4B, but becomes a rounded waveform as indicated by a solid line of for example FIG. 4B due to the effect of the performances of the D/A converter 7, input/output circuit, interface cable, etc. The rounding shown the figure is simple rounding by a primary time constant, but in actuality it becomes a more complex waveform, for example, a waveform accompanied by overshooting. Further, this waveform distortion due to rounding etc. becomes relatively more severe in a monitor having a higher pixel clock and higher degree of precision.
The output of this D/A converter 7 is sampled again by the sample-and-hold circuit 22 (ADC31 in second related art), but if the rear edge portion of the output data of the D/A converter 7 can be sampled well at the timing indicated as a first sample-and-hold (S/H) pulse in for example FIG. 4C, the output thereof becomes relatively faithful to original signal. However, if the front edge portion of the output data of the D/A converter 7 is sampled by a timing as indicated in the second sample-and-hold (S/H) pulse of FIG. 4D, the output thereof becomes remarkably different from the original waveform.
Such a phenomenon is peculiar to computer image output. Namely, this is because a dot of one black pixel or a fine line in a white background and an image reverse to this are extremely ordinary in a text image and graphic image. Note that such a phenomenon does not occur in an image obtained from the camera.
Good management of the timing shown in FIGS. 4A to 4D, however, is not possible in actuality. This is because the pixel clock is not supplied from the personal computer 10 side, therefore usually the pixel clock is reproduced based on the horizontal synchronization signal in the LCD 20. On the other hand, the personal computer 10 side does not manage the phases of the pixel clock of the D/A converter 7 and the horizontal synchronization signal, therefore the pixel clocks of the personal computer 10 side and the LCD 20 side are generated independently from each other. Even if it is desired to manage them, where for example the pixel clock is near 100 MHz, if the required precision is represented by time, it becomes about 1 to 2 ns. Accordingly, the management thereof becomes very difficult. Even if it becomes possible, it is very difficult to reproduce a pixel clock with a precision of 1 to 2 ns from a horizontal synchronization signal of about several tens of kHz on the LCD 20 side.
At the present time, therefore, a manual phase adjustment means is provided on the LCD 20 side, and the phase is appropriately adjusted while viewing the image quality. As a means for making adjusting the phase, conventionally use has been made of a polarity inversion circuit and a variable delay circuit. In very simple apparatuses, there also exists means for adjusting the phase by only polarity inversion, but these are not satisfactory in terms of the image quality.
FIG. 5 shows an example of a typical variable delay circuit using a bipolar transistor circuit. Basically, this is configured as a buffer using a differential type current mode logic (CML) circuit. This inserts a capacity element C between emitters of emitter followers Q5 and Q6 and controls the current Ic by a control voltage Vc so as to control the delay time. The maximum value of the delay obtained by this circuit is 180.degree. converted to a phase. Accordingly, in order to secure a range of adjustment of 180.degree., a structure connecting at least two stages in series is necessary. Since the pixel clock changes, the extent of change of the control current Ic cannot be made too large, and other reasons, the range of adjustment is unexpectedly narrow. Accordingly, in actuality, a structure in which at least four stages to eight stages are connected in series becomes necessary.
However, phase adjustment by such a variable delay circuit of the related art involves some problems. First, in order to handle several types of display modes such as in a multi-scan display, it is necessary for the pixel clock to change over a wide range, but if the extent of change is increased, the required number of stages becomes larger.
Second, the linearity of the control characteristic is very bad. For example, in the variable delay circuit of FIG. 5. one of the reasons of the degraded linearity is basically that the delay time is in inverse proportion to the control current Ic. Further, due to the frequency characteristic of the transistors, particularly the delay time of the differential buffers of the npn transistors Q7 and Q8, even if the control current Ic is increased, the delay time does not become smaller in inverse proportion to this. Note that this phenomenon becomes remarkable particularly when the pixel clock becomes high.
Third, one of the objects of a phase adjustment circuit is high precision phase adjustment, but one of its components, that is, the variable delay circuit, sets the delay time. This means that a change of the pixel clock greatly changes the phase and the range of adjustment thereof. Namely, a great change of the adjustment sensitivity leads to the necessity of excessively raising the resolution over the original adjustment precision where it is desired to give phase adjusted data as the digital data.
Further, fourth, it is also difficult to obtain stable characteristics from the viewpoints of the power supply voltage dependency and the temperature dependency in the phase adjustment circuit of the related art.